Field of the Invention
The present invention relates to display device technology, and more particularly to a source driving circuit.
Description of Prior Art
FIG. 1 shows a schematic diagram of a source driving circuit of a liquid crystal display panel in the prior art, and merely the source driving circuit having a plurality of data channels D1-DN is shown. As shown in FIG. 1, the source driving circuit 10 includes a shift register 11, and further includes a first latch 12, a second latch 13, a level converter 14, a digital to analog converter (DAC) 15, and an output buffer 16 corresponding to each data channel. Specifically, the shift register 11 is electrically connected to the respective first latches 12 on the plurality of data channels. Furthermore, the shift register 11 sequentially selects the first latch 12 of one of the data channels, and then the data signal is transmitted to the corresponding data line. Taking the first and the second data channels as an example, the first latch 12 of the first data channel D1 is, respectively, connected to the second latch 13 of the first data channel D1 and the second latch 13 of the second data channel D2, and the first latch 12 of the second data channel D2 is, respectively, connected to the second latch 13 of the first data channel D1 and the second latch 13 of the second data channel D2.
The first latch 13 of each data channel sequentially is electrically connected to the output buffer 16 through the level converter 14 and the DAC 15. The output buffer 16 of the first data channel D1 is, respectively, electrically connected to an output terminal of the second data channel D2 and an output terminal of the first data channel D1. The output buffer 16 of the second data channel D2 is, respectively, electrically connected to the output terminal of the second data channel D2 and the output terminal of the first data channel D1.
With the development of technology, three or four data are orderly outputted by an identical data channel in order to raise the data transfer rate. As shown in FIG. 2, a white gray-scale data 21, a red gray-scale data 22, a blue gray-scale data 23, and a green gray-scale data 24 (i.e. a structure with channel to gray-scale data ratio 1:4) are outputted on the data channel on the left side of FIG. 2; while a white gray-scale data 26, a red gray-scale data 27, a blue gray-scale data 28, and a green gray-scale data 29 are outputted on the data channel of the right side of FIG. 2. Along with a turning on and a turning off of switches sequentially of channels 41, 42, 43, and 44 in a display panel 30, four data RGBW are outputted with the operations of the switches are sequentially outputted. In this manner, a corresponding data, i.e. a green data, a blue data, a red data and a white data (G, B, R, W), can be sent to a corresponding pixel. That is, the green gray-scale data 24, the blue gray-scale data 23, the red gray-scale data 22, and the white gray-scale data 21 are respectively inputted to a corresponding green pixel 31, a corresponding blue pixel 32, a corresponding red pixel 33, and a corresponding white pixel 34, which are located on the data lines of the display panel 30 on the left side while the green gray-scale data 29, the blue gray-scale data 28, the red gray-scale data 27, and the white gray-scale data 26 are inputted to a corresponding green pixel 35, a corresponding blue pixel 36, a corresponding red pixel 37, and a corresponding white pixel 38, which are located on the data lines of the display panel 30 on the right side. Although the number of data channels of this kind of circuit can be reduced, larger power consumption will be caused when there is a larger difference existing between the gray-scale values of two adjacent pixels, since a plurality of gray-scale data are inputted through an identical data line.
Therefore, it is necessary to provide a source driving circuit to solve the existing problems in the prior art.